Datasheet

DMA CONTROLLER MODULE
MOTOROLA MCF5206e USER’S MANUAL 7-9
BWC—Bandwidth Control
These three bits are decoded to provide for internal bandwidth control. When the byte
count has reached the programmed BWC boundary, the request signal to the internal ar-
biter is negated until the completion of the data access to enable the ColdFire core to ac-
cess the bus.Table 7-8 shows the encodings for these bits. When the bits are cleared, the
DMA does not negate its request. The table shows BCR values at which the bus is relin-
quished. For example, if BWC = 001 and the BCR is set to 516, the bus is relinquished
after four bytes are transferred.
SAA—Single Address Access
1 = The DMA channel is in single address mode. The DMA provides an address from
the SAR and directional control, bit S_RW, to allow two peripherals (one may be
memory) to exchange data within a single access. Data is not stored by the DMA.
0 = The DMA channel is in dual address mode.
S_RW—Single Address Access Read/Write Value.
This bit specifies the value of the external R/W signal during single address accesses.
This provides directional control to the master bus controller.
1 = Forces the external R/W signal to a logic high state.
0 = Forces the external R/W signal to a logic low state.
The bit is only valid when the SAA bit is set.
SINC—Source Increment
This bit controls whether the source address increments after each successful transfer.
1 = The SAR increments by 1, 2, 4, or 16, depending upon the size of the transfer.
0 = There is no change to the SAR after a successful transfer.
SSIZE—Source Size
This field controls the size of the source bus cycle that the DMA Controller Module is run-
ning. See Table 7-4 for the encoding of this field.
Table 7-3. BWC Encoding
BWC BLOCK SIZE
000 Bandwidth Control Disabled
001 512
010 1024
011 2048
100 4096
101 8192
110 16384
111 32768
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