Datasheet

DMA CONTROLLER MODULE
7-10 MCF5206e USER’S MANUAL MOTOROLA
DINC—Destination Increment
This bit controls whether the destination address increments after each successful trans-
fer.
1 = The DAR increments by 1, 2, 4, or 16 depending upon the size of the transfer.
0 = There is no change to the DAR after a successful transfer.
DSIZE—Destination Size
This field controls the size of the destination bus cycle that the DMA Controller Module is
running. See Table 7-10 for the encoding of this field.
START—Start Transfer
1 = Indicates to the DMA to begin the transfer according to the values in the control reg-
isters.
This bit is self-clearing after one clock and is always read as a logic 0.
7.4.5 DMA Status Register (DSR)
The DMA Status Register (DSR) is an 8-bit register that reports on the status of the DMA
Controller Module. On recognition of an event, the DMA Controller Module sets the
corresponding bit in the DSR. Only writes to bit 0 of the DSR have any effect.
NOTE
Setting the DONE bit creates a single-cycle pulse, which will re-
set the channel thus clearing all bits in the register. This must be
done at the completion of a transfer, though it may be set during
a transfer to abort the transfer.
DMA Status Register (DSR)
Table 7-4. SSIZE Encoding
SSIZE TRANSFER SIZE
00 Longword
01 Byte
10 Word
11 Line
Table 7-5. DSIZE Encoding
DSIZE TRANSFER SIZE
00
Longword
01
Byte
10
Word
11
Line
76543210
- CE BES BED - REQ BSY DONE
Reset:
-000-000
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eescale S
emiconduct
or
, I
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