Datasheet

DMA CONTROLLER MODULE
7-12 MCF5206e USER’S MANUAL MOTOROLA
7.4.6 DMA Interrupt Vector Register
The DMA Interrupt Vector Register (DIVR) is an 8-bit register, which is sent to the ColdFire
core in response to an acknowledge cycle. The register is selected when both the SMEN
and SIVOE signals are asserted.
DMA Interrupt Vector Register (DIVR)
7.5 TRANSFER REQUEST GENERATION
The DMA channel supports two types of request generation methods: internal and external.
Both types of requests can be programmed to limit the amount of bus use and can be either
cycle-steal mode or continuous mode. The EEXT field in the DCR programs the request
generation method used for the channel.
7.5.1 Cycle Steal Mode
When the CS field in the DCR is set, the DMA is in cycle-steal mode. This means that only
one complete transfer from source to destination will take place for each request that the
module receives. The request can be either internal or external depending on how the EEXT
field is programmed.
NOTE:
When in cycle steal mode, the DMA channel is forced to give up
the bus. If no external master is requesting the bus and the CPU
is not requesting the bus, the lower priority channel will get 1 ac-
cess to the bus before the higher priority channel gets it back.
However, the more likely scenario that the CPU is also request-
ing access, the higher priority channel keeps ownership until the
transfer is complete.
7.5.2 Continuous Mode
If the CS field in the DCR is cleared, the DMA is in continuous mode. After a request is
asserted, either internal or external, the DMA continuously transfers data until the BCR is
zero, the value in the BWC is reached, or the DONE bit in the DSR is set.
The continuous mode can be run at either the maximum rate or a limited rate. The maximum
rate of transfer can be achieved if the BWC field in the DCR is programmed to be 000. Then
the DMA channel that has started a transfer will continue until the BCR decrements to zero
or a 1 is written to the DONE bit in the DSR.
A limited rate can be achieved by programming the BWC field to be anything except 000.
The DMA then performs the specified number of transfers and surrenders the bus to allow
another device to use the bus. In this mode, the DMA negates its internal bus request on the
76543210
Interrupt Vector Bits
Reset:
00001111
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