Datasheet

DMA CONTROLLER MODULE
MOTOROLA MCF5206e USER’S MANUAL 7-13
last transfer before the boundary programmed in the BWC field. After the transfer is
complete, it then asserts its internal bus request again to regain mastership at the earliest
possible time as determined by the internal bus arbiter. The minimum amount of time that
the DMA does not have the bus is one bus cycle.
7.6 DATA TRANSFER MODES
Each DMA channel supports single- and dual-address transfers. The single-address trans-
fer mode consists of one DMA bus cycle, which allows either a read or a write cycle to occur.
The dual-address transfer mode consists of a source operand read and a destination oper-
and write.
7.6.1 Single Address Transactions
The DMA Controller Module begins a single address transfer sequence when the SAA bit is
set while a DMA request is made. If no error conditions exist, the REQ bit is set. When the
channel is enabled, the BSY bit is set and the REQ bit is cleared. The SAR contents are then
driven onto the address bus and the value of the S_RW bit is driven onto the R/W signal.
The BCR decrements on successful address phase accesses until it reaches 0, and the
DONE bit is set.
In the event of a termination error, the BES and DONE bit of the DSR are set, and no further
DMA Controller Module transactions are attempted.
7.6.2 Dual Address Transactions
The DMA Controller Module begins a dual-address transfer sequence when the SAA bit is
cleared while a DMA request is made. If no error condition exists, the REQ bit of the DSR is
set.
7.6.2.1 DUAL ADDRESS READS. The DMA Controller Module drives the value in the SAR
onto the address bus. If the SINC bit of the DCR is set, then the SAR increments by the
appropriate number of bytes upon a successful read cycle. When the appropriate number of
read cycles completes successfully, the DMA initiates the write portion of the transfer.
In the event of a termination error, the BES and DONE bit of the DSR are set, and no further
DMA Controller Module transactions are attempted.
7.6.2.2 DUAL ADDRESS WRITES. The DMA Controller Module drives the value in the
DAR onto the address bus. If the DINC bit of the DCR is set, the DAR increments by the
appropriate number of bytes at the completion of a successful write cycle. The BCR
decrements by the appropriate number of bytes. If the BCR equals zero, the DONE bit is set.
If the BCR is greater than 0, then another read/write transfer is initiated. If the BCR is a
multiple of the programmed BWC, then the DMA request signal is negated until termination
of the bus cycle, to allow the internal arbiter to return control to the ColdFire core. There is
an idle clock before the next assertion of MTS.
In the event of a termination error, the BED and DONE bit of the DSR are set, and no further
DMA Controller Module transactions are attempted.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...