Datasheet

DMA CONTROLLER MODULE
7-14 MCF5206e USER’S MANUAL MOTOROLA
7.7 DMA CONTROLLER MODULE FUNCTIONAL DESCRIPTION
In the following descriptions, “DMA request” implies that the START bit is set or the DREQ
signal is asserted while the EEXT bit is set. The START bit is cleared when the channel
begins an internal access. Before initiating a transfer request, the DMA Controller Module
first verifies that the source size and destination size (dual address only) as configured in
the DCR, are consistent with the source address and destination address. If a misalignment
is detected, no transfer occurs, and the CE bit of the DSR is set. The CE bit is also set if the
BCR contains a value inconsistent with both the destination size (dual address only) and the
source size. Depending on the configuration of the DCR, an interrupt event may be issued
when the CE bit is set. Note that if the AA bit is set, error checking is performed only on the
appropriate registers.
A “read/write” transfer refers to a dual-address access in which a number of bytes are read
from the source address and written to the destination address. The number of bytes
transferred is determined by the larger of the sizes specified by the source and destination
size encodings.
The source and destination address registers (SAR and DAR) increment at the completion
of a successful address phase. The BCR decrements at the completion of a successful
address phase write when SAA=0 or any successful address phase when SAA=1. A
successful address phase occurs when a valid address request is not held by the arbiter.
7.7.1 Channel Initialization and Startup
Before starting a block transfer operation, the channel registers must be initialized with infor-
mation describing the channel configuration, request generation method, and data block.
This initialization is accomplished by programming the appropriate information into the
channel registers.
7.7.1.1 CHANNEL PRIORITIZATION. Channel 0 has priority over Channel 1 unless
overwritten by the BWC bits in channel 1’s DCR. If the BWC bits for DMA channel 1 are set
to 000, then it will have priority over channel 0, unless channel 0 also has the BWC bits set
to 000.
7.7.1.2 PROGRAMMING THE DMA CONTROLLER MODULE. Some general comments
on programming the DMA follow:
• No mechanism exists for preventing writes to control registers during DMA accesses
• If the BWC of sequential channels are equivalent, channel priority is in ascending order
The SAR is loaded with the source (read) address. If the transfer is from a peripheral device
to memory, the source address is the location of the peripheral data register. If the transfer
is from memory to a peripheral device or memory to memory, the source address is the start-
ing address of the data block. This address may be any byte address. In the single-address
mode, this register is used regardless of the direction of the transfer.
The DAR should contain the destination (write) address. If the transfer is from a peripheral
device to memory or memory to memory, the DAR is loaded with the starting address of the
data block to be written. If the transfer is from memory to a peripheral device, the DAR is
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