Datasheet

DMA CONTROLLER MODULE
MOTOROLA MCF5206e USER’S MANUAL 7-15
loaded with the address of the peripheral data register. This address may be any byte
address. In the single-address mode, this register is not used.
The manner in which the SAR and DAR change after each cycle depends on the values in
the DCR SSIZE and DSIZE fields and the SINC and DINC bits, and the starting address in
the SAR and DAR. If programmed to increment, the increment value is 1, 2, 4, or 16 for byte,
word, longword, or line operands, respectively. If the address register is programmed to
remain unchanged (no count), the register is not incremented after the operand transfer.
The BCR must be loaded with the number of byte transfers that are to occur. This register
is decremented by 1, 2, 4, or 16 at the end of each transfer. The DSR must be cleared for
channel startup.
Once the channel has been initialized, it is started by writing a one to the START bit in the
DCR or asserting the DREQ signal, depending on the status of the EEXT bit in the DCR.
Programming the channel for internal request causes the channel to request the bus and
start transferring data immediately. If the channel is programmed for external request,
DREQ must be asserted before the channel requests the bus.
If any fields in the DCR are modified while the channel is active, that change is effective
immediately. To avoid any problems with changing the setup for the DMA channel, a 1
should be written to the DONE bit in the DSR to stop the DMA channel.
7.7.2 Data Transfers
7.7.2.1 EXTERNAL DMA REQUEST OPERATION. Each channel has the feature of
interfacing to an external device to initiate transfers to the device. If the EEXT bit is set, when
the DREQ signal asserts, the DMA initiates a transfer provided the channel is idle. If the CS
(cycle steal) bit is set, then a single read/write transfer occurs. If the CS bit is clear, multiple
read/write transfers occur as programmed. The DREQ signal is not required to be negated
until the DONE bit of the DSR asserts. In cycle-steal mode, the maximum length of DREQ
assertion to maintain a single transfer depends on configuration. In the worst case of a
single-address access, byte accesses, and idle channels, DREQ may be asserted for no
more than five rising clock edges (see Figure 7-5).
Figure 7-5. External Request Timing - Cycle Steal Mode, Single-Address Mode
See Figure 7-7 for timing relationships for a dual-address transfer using cycle-steal mode.
The maximum assertion time for DREQ
in this configuration is eight clocks.
CLOCK
DREQ[1:0]
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