Datasheet

DMA CONTROLLER MODULE
7-16 MCF5206e USER’S MANUAL MOTOROLA
NOTE:
You can DMA from on-chip serial ports using the UART interrupt
signal as the source for external DMA requests (DREQ). The
mechanism to accomplish this is to configure the Pin Assign-
ment Register (PAR) bits 8 & 9 to the timer function. By doing
this, the DMA external request line is sourced from the UART in-
terrupts. By setting up the UART to interrupt appropriately and
by enabling external requests, the DMA can operate directly
from the UARTs.
When an access occurs that was initiated by an DREQ signal, the transfer mode signals
indicate a DMA cycle, while the transfer modifier signals will indicate that the cycle is due to
an external request. To create an external DMA acknowledge signal, it may be necessary
to decode the address of the peripheral along with a combination of the transfer mode and
transfer type signals. To create an external DMA acknowledge signal for block transfers, you
may count the transfers or compare the address to a stored final address to assert the DMA
acknowledge to the peripheral.
Figure 7-6. External Request Timing - Cycle Steal Mode, Dual Address Mode
7.7.2.2 AUTO-ALIGNMENT. This feature allows for block transfers to occur at the most
optimum size possible based on the address, byte count, and programmed size. To use this
feature, AA in the DCR must be set. The source is auto-aligned when the SSIZE bits indicate
a larger transfer size compared to DSIZE. Source alignment takes precedence over the
destination when the source and destination sizes are equal. Otherwise, the destination is
auto-aligned. The address register that is chosen for alignment increments regardless of the
value of the increment bit. Configuration error checking is performed on the registers that
are not chosen for alignment.
If the BCR contains a value greater then 16, the address determines the size of the transfer.
Single byte, word or longword transfers occur until the address is aligned to the programmed
size boundary, at which time the programmed size accesses begin. When the BCR is less
than 16 at the beginning of a read/write transfer, the number of bytes remaining will dictate
the transfer size, longword, word or byte.
For example,
CLOCK
EXT_REQ[3:0]
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