Datasheet

DMA CONTROLLER MODULE
MOTOROLA MCF5206e USER’S MANUAL 7-17
AA = 1, SAR = $0001, BCR = $00F0, SSIZE = 00 (longword) and DSIZE = 01 (byte),
Because the SSIZE > DSIZE, the source is auto-aligned. Error checking is performed on the
destination registers. The sequence of accesses is as follows:
• Read byte from $0001 - write byte, increment SAR
• Read word from $0002 - write 2 bytes, increment SAR
• Read long word from $0004 - write 4 bytes, increment SAR
• Repeat longwords until SAR = $00F0
• Read byte from $00F0 - write byte, increment SAR.
If DSIZE is set to another size, then the data writes are optimized to write the largest size
allowed based on the address, but not exceeding the configured size.
NOTE
If AA is set, the BCR may skip over the programmed boundary.
In this case, the DMA master bus request will not negate.
7.7.2.3 BANDWIDTH CONTROL. This feature provides a mechanism that can force the
DMA to relinquish control to the ColdFire core. The decode of the BWC provides 7 levels of
block transfer sizes. If the BCR decrements to a value equivalent to the decode of the BWC,
the DMA master bus request negates until termination of the bus cycle. The arbiter may then
choose to switch the bus to another master, should a request be pending. If the BWC = 0,
the request signal will remain asserted until the BCR reaches 0. In addition, an internal
signal will assert to indicate that the channel has been programmed to have priority. Note
that in this arbitration scheme, the arbiter always has the capability to force the DMA to
relinquish the bus.
7.7.3 Channel Termination
7.7.3.1 ERROR CONDITIONS. When the DMA Controller Module encounters a read or
write cycle that terminates with an error condition, the appropriate bit of the DSR is set,
depending on whether the bus cycle was a read (BES) or a write (BED). The DMA transfers
are then halted. If the error condition occurred during a write cycle, any data remaining in
the internal holding register is lost.
7.7.3.2 INTERRUPTS. If the INT bit of the DCR is set, the DMA will drive the appropriate
slave bus interrupt signal. A processor can then read the DSR to determine if the transfer
terminated successfully or with an error. The DONE bit of the DSR is then written with a 1
to clear the interrupt, along with clearing the DONE and error bits.
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