Datasheet

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MOTOROLA MCF5206e USER’S MANUAL 8-1
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SECTION 8
SYSTEM INTEGRATION MODULE
8.1 INTRODUCTION
This subsection details the operation and programming model of the System Integration
Module (SIM) registers, including the interrupt controller and system-protection functions for
the MCF5206e. The SIM provides overall control of the internal and external buses and
serves as the interface between the ColdFire
®
core processor and the internal peripherals
or external devices.
8.1.1 Features
The following list summarizes the key SIM features:
• Module Base Address Register (MBAR)
— Base address location of all internal peripherals and SIM resources
— Address space masking to internal peripherals and SIM resources
• Interrupt Controller
— Programmable interrupt level (1-7) for internal peripheral interrupts
— Programmable priority level (0-3) within each interrupt level
— Three external interrupts - programmable as individual Interrupt Requests or as
Interrupt Priority-Level signals
• System Protection
— Reset status to indicate cause of last reset
— Bus monitor and Spurious Interrupt Monitor
— Software Watchdog Timer
• Internal Bus Arbitration
— Arbitration for internal bus between ColdFire core processor and DMA modules
8.2 SIM OPERATION
8.2.1 Module Base Address Register (MBAR)
The MBAR determines the base address of all internal peripherals as well as the definition
of which types of accesses are allowed for these registers.
The MBAR is a 32-bit write-only supervisor control register. It is accessed in the CPU
address space $C0F via the MOVEC instruction. (Refer to the ColdFire Microprocessor
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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