Datasheet

System Integration Module
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System Integration Module
8-2 MCF5206e USER’S MANUAL MOTOROLA
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Family Programmer’s Reference Manual (MCF5200PRM/AD) for use of MOVEC
instruction). The MBAR can be read when in debug mode using background debug
commands.
At system reset, the MBAR valid bit is cleared to prevent incorrect references to resources
before the MBAR is written. The remainder of the MBAR bits are uninitialized. To access the
internal peripherals, you should write MBAR with the appropriate base address and set the
valid bit after system reset.
All internal peripheral registers occupy a single relocatable memory block along 1 KByte
boundaries. If the MBAR valid bit is set, the base address field is compared to the upper 22
bits of the full 32-bit internal address to determine if an internal peripheral is being accessed.
The MBAR masks specific address spaces using the address space fields. Any attempt to
access a masked address space results in an access being generated on the external bus.
8.2.2 Bus Timeout Monitor
The bus monitor ensures that each external cycle terminates within a programmed period of
time. It continually checks the external bus for termination and asserts the internal transfer
error acknowledge that results in an access fault exception if the response time is greater
than the programmed bus monitor time. If a transfer is in progress while TEA is asserted,
the transfer is aborted and the exception will occur.
You can program the bus monitor time to 128, 256, 512, or 1024 clock cycles using the bus
monitor timing bits in the system protection control register (SYPCR). The value you select
should be larger than the longest possible response time of the slowest peripheral of the
system. The bus time-out monitor begins counting on the clock cycle TS is asserted and
stops counting on the clock after the assertion of the final transfer termination signal (i.e., for
a line transfer to a 32-bit port, the bus time-out monitor starts counting on the clock TS is
asserted and stops counting after TA and/or ATA have been asserted a total of four times).
The bus monitor enable bit in the SYPCR enables the bus monitor for external bus cycles.
The bus monitor cannot be disabled for internal bus cycles to internal peripherals. Once the
SYPCR is written using the MOVEC instruction, the state of the bus time-out monitor cannot
be changed—the SYPCR may be written only once. Refer to subsection 8.3.2.7 System
Protection Control register (SYPCR) for programming information.
8.2.3 Spurious Interrupt Monitor
The SIM automatically generates the spurious interrupt vector number 24 ($18), which
causes the ColdFire core processor to terminate the cycle with a spurious interrupt
exception if:
• An external device responds to an interrupt acknowledge cycle by asserting TEA
• No interrupt is pending for the interrupt level being acknowledged when the interrupt
acknowledge cycle is generated
Fr
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Freescale Semiconductor, Inc.
For More Information On This Product,
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