Datasheet

System Integration Module
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System Integration Module
MOTOROLA MCF5206e USER’S MANUAL 8-3
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NOTE
If an external device does not respond to an interrupt
acknowledge cycle by asserting TA or ATA, an access error
exception will be generated, not a spurious interrupt exception.
To generate a spurious interrupt exception, TEA would have to
be generated.
8.2.4 Software Watchdog Timer
The software watchdog timer (SWT) prevents system lockup in case the software becomes
trapped in loops with no controlled exit. The SWT can be enabled via the software watchdog
enable bit in the SYPCR. If enabled, the SWT requires a special service sequence execution
on a periodic basis. If this periodic servicing action does not occur, the SWT times out and
results in a hardware reset or a level 7 interrupt, as programmed by the software watchdog
reset/interrupt select bit in the SYPCR. If the SWT times out and is programmed to generate
a hardware reset, an internal reset will be generated and the software watchdog timer reset
bit in the reset status register is set. Additionally, if the RTS2/RSTO pin is programmed for
RSTO, RSTO is asserted for 32 CLK cycles. Refer to subsection 8.3.2.10 Pin Assignment
Register (PAR) for more information on programming.
The 8-bit interrupt vector for the SWT interrupt is stored in the software watchdog interrupt
vector register (SWIVR). The software watchdog prescalar (SWP) and software watchdog
timing (SWT) bits in SYPCR determine the SWT time-out period.
The SWT service sequence consists of these two steps: write $55 to SWSR, and write $AA
to the SWSR. Both writes must occur in the order listed prior to the SWT time-out, but any
number of instructions or accesses to the SWSR can be executed between the two writes.
This order allows interrupts and exceptions to occur, if necessary, between the two writes.
NOTE
If the SYSPCR is programmed for the SWT to generate an
interrupt and the SWT times out, the SWT must be serviced in
the interrupt handler routine by writing the $55, $AA sequence to
the SWSR.
8.2.5 Interrupt Controller
The SIM provides a centralized interrupt controller for all MCF5206e interrupt sources,
including:
• External Interrupts (IPL/IRQ)
• Software watchdog timer
• Timer modules
•MBUS (I
2
C) module
•UART modules
•DMA modules
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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