Datasheet
System Integration Module
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
System Integration Module
8-4 MCF5206e USER’S MANUAL MOTOROLA
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
All interrupt inputs are level sensitive. An interrupt request must be held valid for at least two
consecutive CLK periods to be considered a valid input. The three external interrupt inputs
can be programmed to be three individual interrupt inputs (at level 1, 4, and 7) or encoded
interrupt priority levels.
NOTE
If the external interrupt inputs are programmed to individual
interrupt requests (at level 1, 4, and 7), the interrupt request
must be asserted until the MCF5206e acknowledges the
interrupt (by generating an interrupt acknowledge cycle) to
guarantee that the interrupt is recognized.
If the external interrupt inputs are programmed to be interrupt priority levels, the interrupt
request must maintain the interrupt request level or a higher priority level request until the
MCF5206e acknowledges the interrupt to guarantee that the interrupt is recognized.
When the external interrupts are programmed to be individual IRQ interrupts in the Pin
Assignment Register (PAR), the interrupt level bits in the appropriate ICRs of the external
interrupts are not user-programmable and are always set to 1, 4, and 7. The value of the
interrupt level bits in the ICRs for the external interrupts cannot be changed, even by a write
to the register.
If the external interrupts are programmed to be encoded interrupt priority levels, the interrupt
level is that indicated as shown in Table 8-1.
Although the interrupt levels of the external interrupts are fixed, customers can program the
interrupt priorities of the external interrupts to any value using the IP (IP1, IP0) bits in the
corresponding interrupt control registers (ICR7 - ICR1). You can program the autovector bits
in the interrupt control registers and you should program them to 1 when autovector
generation is preferred.
NOTE
When an autovectored interrupt occurs, the interrupt is serviced
internally. No external IACK cycle occurs.
Table 8-1. Interrupt Levels for Encoded External Interrupts
IPL[2]/IRQ[7] IPL[1]/IRQ[4] IPL[0]/IRQ[1]
INTERRUPT LEVEL
INDICATED
000 7
001 6
010 5
011 4
100 3
101 2
110 1
1 1 1 No Interrupt
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
