Datasheet

System Integration Module
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System Integration Module
MOTOROLA MCF5206e USER’S MANUAL 8-5
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The Software Watchdog Timer (SWT) has a fixed interrupt level (level 7). The interrupt
priority of the SWT can be programmed to any value using the IP (IP1, IP0) bits in the SWT
interrupt control register, ICR8. You cannot program the SWT to generate an autovector.The
autovector bit in ICR8 is reserved and is always set to zero. The value of the software
watchdog interrupt vector register is always be used as the interrupt vector number for a
SWT interrupt.
You can program the timer modules’ interrupt levels and priorities using the interrupt level
(IL2 - IL0) and interrupt priority (IP1, IP0) bits in the appropriate interrupt control registers
(ICR9, ICR10). The timer peripherals cannot provide interrupt vectors. Thus, autovector bits
in ICR9 and ICR10 are always set to 1. This generates autovectors in response to all timer
interrupts.
You can also program the MBUS module interrupt level and priority using the interrupt level
(IL2 - IL0) and interrupt priority (IP1, IP0) bits in the MBUS interrupt control register, ICR11.
You cannot program the MBUS module to provide an interrupt vector. Thus, the autovector
bit in ICR11 is always set to 1. This generates an autovector in response to an MBUS
interrupt.
You can program the UART modules’ interrupt levels and priorities using the interrupt level
(IL2 - IL0) and interrupt priority (IP1, IP0) bits in the appropriate interrupt control registers
(ICR12, ICR13). In addition, you can program the autovector bits in ICR12 and ICR13. If the
autovector bit is set to 0, you must program the interrupt vector register in each UART
module to the preferred vector number.
The interrupt controller monitors and masks individual interrupt inputs and outputs the
highest priority unmasked pending interrupt to the ColdFire core. Each interrupt input has a
mask bit in the Interrupt Mask Register (IMR) and a pending bit in the interrupt pending
register (IPR). The pending bits for all internal interrupts in the interrupt pending register are
set the CLK cycle after the interrupt is asserted whether or not the interrupt is masked. If you
program the external interrupt inputs as individual interrupt inputs, the pending bits in the
interrupt pending register are set to the CLK cycle after the interrupt is asserted and
internally synchronized.
If you program the external interrupt inputs to indicate interrupt priority levels, the interrupt
pending bits are set and cleared as follows:
1. The interrupt pending bits, EINT[7:1] are set to the CLK cycle after the interrupt level
has been internally synchronized and indicated the same valid level for two
consecutive CLK cycles.
2. EINT[7:1] remains set if the external interrupt level remains the same or increases in
priority.
3. The interrupt pending bits EINT[7:1] are cleared if the external interrupt level
decreases in priority or if an interrupt acknowledge cycle is completed for an external
interrupt that is pending but is not the current level being driven onto the external
interrupt priority level signals (IPLx/IRQx).
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Freescale Semiconductor, Inc.
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