Datasheet

System Integration Module
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System Integration Module
8-6 MCF5206e USER’S MANUAL MOTOROLA
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You can assign as many as four interrupts to the same interrupt level, but you must assign
unique interrupt priorities. The interrupt controller uses the interrupt priorities during an
interrupt acknowledge cycle to determine which interrupt is being acknowledged. The
interrupt priority bits determine the appropriate interrupt being acknowledged when multiple
interrupts are assigned to the same level and are pending when the interrupt-acknowledge
cycle is generated.
NOTE
You should not program interrupts to have the same level and
priority. Interrupts can have the same level but different
priorities. All level and priority combinations must be unique.
If an external interrupt request is being acknowledged and the AVEC bit in the
corresponding ICR is not set, an external interrupt acknowledge cycle occurs. During an
external interrupt acknowledge cycle, TT[1:0] and A[27:5] are driven high; A[4:2] are set to
the interrupt level being acknowledged; and A[1:0] are driven low. Additionally, ATM is
asserted when TS is asserted and ATM is negated when TS is negated. For nonautovector
responses, the external device places the vector number on D[31:24]. For autovector
responses, the autovector is generated internally and no external interrupt acknowledge
cycle is run.
An interrupt request from the SWT does not require an external interrupt acknowledge cycle
because SWIVR stores its interrupt vector number.
If an internal peripheral interrupt source is being acknowledged and the AVEC bit in the
corresponding ICR is cleared, an internal interrupt-acknowledge cycle occurs with the
internal peripheral supplying the interrupt vector number. If the corresponding AVEC bit is
set, an internal interrupt-acknowledge cycle run but the SIM internally generates an
autovector. No external interrupt acknowledge cycle is run.
8.3 PROGRAMMING MODEL
8.3.1 SIM Registers Memory Map
Table 8-2 shows the memory map of all the SIM registers. The internal registers in the SIM
are memory-mapped registers offset from the MBAR address pointer. The following list
addresses several key notes regarding the programming model table:
• The Module Base Address Register can only be accessed in supervisor mode using the
MOVEC instruction with an Rc value of $C0F.
• Underlined registers are status or event registers.
• Addresses not assigned to a register and undefined register bits are reserved for future
expansion. Write accesses to these reserved address spaces and reserved register bits
have no effect; read accesses returns zeros.
• The reset value column indicates the register initial value at reset. Certain registers may
be uninitialized at reset.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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