Datasheet

System Integration Module
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System Integration Module
MOTOROLA MCF5206e USER’S MANUAL 8-9
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• Operation of bus time-out monitor when the internal freeze signal is asserted
• Operation of bus lock.
The internal freeze signal is asserted when the core processor has entered into Background
Debug mode (BDM) for software development purposes.
The SIMR is an 8-bit read-write register. At system reset, FRZ1 and FRZ0 are set to 1 and
BL is set to 0.
FRZ1 - Freeze Software Watchdog Timer Enable
0 = When the internal freeze signal is asserted, the software watchdog timer continues
to run.
1 = When the internal freeze signal is asserted, the software watchdog timer is disabled.
FRZ0 - Freeze Bus Timeout Monitor Enable
0 = When the internal freeze signal is asserted, the bus timeout monitor continues to
run.
1 = When the internal freeze signal is asserted, the bus timeout monitor is disabled.
BL - Bus Lock Enable
Bus lock enable lets customers control the assertion and negation of the bus driven (BD)
signal. Refer to the Bus Operation section for more information.
0 = Bus Driven (BD) signal is negated by the MCF5206e and the bus is released when
bus grant (BG) is negated and the current bus cycle is completed.
1 = Once bus grant (BG) is asserted, the bus driven (BD) signal is asserted and can not
be cleared until the BL bit is cleared.
8.3.2.3 INTERRUPT CONTROL REGISTER (ICR). The ICR contains the interrupt levels
and priorities assigned to each interrupt input. There is one ICR for each interrupt input.
Table 8-3 indicates the interrupt control register assigned to each interrupt input, the
interrupt control register reset value, and the value of the interrupt level assigned. Each
interrupt input must have a unique interrupt level and interrupt priority combination.
NOTE
The interrupt control registers do not have valid interrupt level/
interrupt priority combinations out of reset. You must program all
interrupt control registers before programming the interrupt
mask register (IMR). If you program the external interrupt inputs
to be individual interrupts at level 1, 4 and 7, then ICR2, ICR3,
ICR5 and ICR6 are not used.
FRZ1FRZ0-----BL
76543210
11000000
RESET:
SIM Configuration Register(SIMR)
Address MBAR + $03
R/W
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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