Datasheet

System Integration Module
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System Integration Module
MOTOROLA MCF5206e USER’S MANUAL 8-13
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The IPR bit is cleared at the end of the interrupt acknowledge cycle. You cannot write to the
IPR to clear any of the IPR bits.
An active interrupt request appears as a set bit in the IPR, regardless of the setting of the
corresponding mask bit in the IMR.
The IPR is a 16-bit read-only register. At system reset, all bits are initialized to zero.
8.3.2.6 RESET STATUS REGISTER (RSR). The RSR contains a bit for each reset source
to the SIM. A set bit indicates the last type of reset that occurred. The RSR is updated by
the reset control logic when the reset is complete. Only one bit is set at any one time in the
RSR. You can clear this register by writing a one to that bit location; writing a zero has no
effect.
The RSR is an 8-bit read-write register.
HRST - Hard Reset or System Reset
1 = The last reset was caused by an external device driving RSTI. Assertion of reset by
an external device causes the core processor to take a reset exception. All
registers in internal peripherals and the SIM are reset.
SWTR - Software Watchdog Timer Reset
1 = The last reset was caused by the software watchdog timer. If SWRI in the SYPCR
is set and the software watchdog timer times out, a hard reset occurs. RSTO is
asserted as an output.
8.3.2.7 SYSTEM PROTECTION CONTROL REGISTER (SYPCR). The SYPCR controls
the software watchdog timer and bus timeout monitor enables and time-out periods.
DMA 1 DMA 0 UART 2 UART 1 MBUS TIMER 2 TIMER 1 SWT EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 -
1514131211109876543210
0000000000000000
RESET:
Interrupt Pending Register (IPR)
Address MBAR + $3A
Read Only
HRST-SWTR-----
76543210
1/001/000000
RESET:
Address MBAR + $40Reset Status Register(RSR)
R/W
Fr
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Freescale Semiconductor, Inc.
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