Datasheet

System Integration Module
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System Integration Module
8-14 MCF5206e USER’S MANUAL MOTOROLA
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The SYPCR is an 8-bit read-write register. The register can be read at anytime, but can be
written only once after system reset. Subsequent writes to the SYPCR has no effect. At
system reset, the software watchdog timer and the bus timeout monitor are disabled.
SWE - Software Watchdog Enable
0 = Disable the software watchdog timer
1 = Enable the software watchdog timer
SWRI - Software Watchdog Reset/Interrupt Select
0 = Software watchdog timeout generates a level 7 interrupt to the core processor
1 = Software watchdog timeout generates an internal reset and RSTO is asserted
NOTE
If SWRI is set to 1, you must set bit 7 in the pin assignment
register (PAR) to have RSTO asserted at the pin during a
software watchdog timer-generated reset. See subsection
8.3.2.10 Pin Assignment Register (PAR) for programming
information.
SWP - Software Watchdog Prescalar
0 = Software watchdog timer clock is not prescaled
1 = Software watchdog timer clock is prescaled by a value of 512
SWT[1:0] - Software Watchdog Timing
These bits (along with the SWP bit) select the timeout period for the software watchdog timer
as shown in Table 8-6. At system reset the software watchdog timing bits are set to the
SWE SWRI SWP SWT1 SWT0 BME BMT1 BMT0
76543210
0 0000000
RESET:
System Protection Control Register(SYPCR)
Address MBAR + $41
R/Write Once
Fr
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Freescale Semiconductor, Inc.
For More Information On This Product,
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