Datasheet

System Integration Module
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
System Integration Module
8-18 MCF5206e USER’S MANUAL MOTOROLA
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
8.9 BUS ARBITRATION CONTROL
8.9.1 Bus Master Arbitration Control (MARB)
The MARB determines the internal master bus arbitration. It selects the highest master, and
can also disable arbitration.
The MPARK is an 8-bit read-write register:
Default Bus Master Register (MPARK)
The internal bus master arbiter uses a very simple algorithm for arbitration; arbitration is
based solely on priority. For as long as the highest priority master continues to request the
internal bus, it receives control of the bus. When the highest priority master relinquishes
control of the bus, another master can take full control of the bus, but it would have to
relinquish control once a higher priority request was received. No master can preempt an
active bus-transaction, however. Once a bus cycle is started, arbitration does not change
until that cycle is complete.
For the most part, the operation of the arbiter is invisible. In fact, code written for any V2
ColdFire microprocessor with no other internal masters will work without modification, since
the default configuration places the core at the highest priority. Priority must be taken,
however, when prioritizing non-core master devices, such as the internal DMA, which must
arbitrate for the bus. The arbitration algorithm used could effectively starve any master not
0110 WE0 CS6 A25 A24
0111 WE0 A26 A25 A24
1000 CS7 CS6 CS5 CS4
1001 CS7 CS6 CS5 A24
1010 CS7 CS6 A25 A24
1011 CS7 A26 A25 A24
1100 A27 A26 A25 A24
1101 Reserved
1110 Reserved
1111 Reserved
Table 8-8. PAR3 - PAR0 Pin Assignment (Continued)
PAR[3:0] A27/CS7/WE0 A26/CS6/WE1 A25/CS5/WE2 A24/CS4/WE3
----NOARB ARBCTRL --
76543210
00000000
RESET:
Bus Master Arbitration Control (MARB)
Address MBAR + $07
Read/Write
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...