Datasheet

System Integration Module
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System Integration Module
MOTOROLA MCF5206e USER’S MANUAL 8-19
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set to the top priority if a higher priority master constantly demands the bus. Possible
solutions to this problem are:
• Changing the ARBCTRL setting at regular intervals to allow for different masters to
share the highest priority.
• Using lower priority masters for “non-essential” tasks which can be completed in the idle
bus cycles of the top priority master.
• Writing code which executes from the instruction cache or single-cycle on-chip SRAM
and therefore provides more idle bus cycles for other masters to use.
The internal arbiter has been specifically designed to recognize bus cycles that hit in the
cache and are prematurely terminated. These killed cycles often happen sequentially as the
processor executes a line from the cache. When the arbiter sees an instruction fetch that
has been killed, it will lower the priority of the ColdFire core for the next bus cycle. This
allows the DMA channels to utilize bus bandwidth the ColdFire core would otherwise be
wasting. The DMA channels should always use the largest transfer of which they are
capable, to transfer the most data in any opportunity. When using interrupts, caution should
be exercised if the ColdFire core is not the highest priority and not immediately able to
answer the interrupt. This could result in a spurious interrupt condition. Use of the Bus
Timeout Monitor is always recommended for use with non-core masters, since it can provide
a method of escaping a master requesting bad transfers.
The NOARB bit simply disables arbiter operation. Setting the NOARB bit causes the
MCF5206e to behave similarly to the MCF5206, however DMA transfers are not now
allowed, since the DMA channels cannot arbitrate for the bus. This functionality has been
provided primarily for customers upgrading older MCF5206 designs where the DMA would
not be used.
NOARB - Arbiter operation disable.
0 = Arbitration enabled
1 = Arbitration disabled (MCF5206 mode)
The ARBCTRL bit determines the highest priority on the internal master bus. These options
are shown in table 8-9:
Table 8-9. Arbitration Control Encodings (ARBCTRL)
ARBCTRL - Set the arbitration priority for the internal master bus.
0 = Arbitration order = ColdFire Core, Internal DMA channels
1 = Arbitration order = Internal DMA channels, ColdFire Core
ARBCTRL
HIGHEST PRIORITY
BUS MASTER
LOWEST PRIORITY
BUS MASTER
0 ColdFire Core Internal DMA Channels
1 Internal DMA Channels ColdFire Core
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Freescale Semiconductor, Inc.
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