Datasheet

Chip Select Module
MOTOROLA MCF5206e USER’S MANUAL 9-5
interface to SRAM, EPROM, EEPROM and peripherals. Each of the eight chip select
outputs has an address register, mask register and control register providing individual16-
bit address decode, 16-bit address masking, port size and burst capability indication, wait-
state generation, automatic acknowledge generation as well as address setup and
address hold features.
Chip selects 0 and 1 provide special functionality. Chip selecthip select 0 is a “global” chip
select after reset that provides relocatable boot ROM capability. Chip select 1 can be
programmed to assert during CPU space accesses including interrupt acknowledge
cycles.
The chip select controller also provides a control register for “default memory,” which is
all of the memory space that is not defined by a chip select or DRAM bank. The default
memory control register lets you program features of the default bus transfer including
port size, burst capability, and wait-state generation.
9.3.1 Chip Select Bank Definition
The general-purpose chip selects are controlled by the Chip Select Address Register
(CSAR), Chip Select Mask Register (CSMR), and the Chip Select Control Register
(CSCR). There is one CSAR, one CSMR, and one CSCR for each chip select signal
generated.
9.3.1.1 BASE ADDRESS AND ADDRESS MASKING. The transfer address generated
by the ColdFire core or by an external master is compared to the unmasked bits of the
base address programmed for each chip select bank in the Chip Select Address Registers
(CSAR0 - CSAR7). The masked address bits are controlled by the value programmed in
the BAM field in the Chip Select Mask Registers (CSMR0 - CSMR7).
The masking of address bits defines the address space of the chip select bank. Address
bits that are masked are not used in the comparison with the transfer address. The base
address field (BA31-BA16) in the CSARs and the base address mask field (BAM31-
BAM16) in the CSMRs correspond to transfer address bits 31-16. Clearing all bits in the
BAM field makes the address space 64 kbyte. For the address space of a chip select bank
to be contiguous, address bits should be masked (BAM bits set to a 1) in ascending order
starting with A[16].
NOTE
The MCF5206e compares the address for the current bus
transfer with the address and mask bits in the Chip Select
Address Registers (CSARs), DRAM Controller Address
Registers (DCARs), the Chip Select Mask Registers
(CSMRs), and DRAM Controller Mask Register (DCMRs),
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...