Datasheet

Chip Select Module
9-6 MCF5206e USER’S MANUAL MOTOROLA
looking for a match.
The priority is listed in Table 9-3 (from highest priority to
lowest priority):
The MCF5206e compares the address and mask in chip
select 0 - 7 (chip select 0 is compared first), then the address
and mask in DRAM 0 - 1. If the address does not match in
either or these, the MCF5206e uses the control bits in the
Default Memory Control Register (DMCR) to control the bus
transfer. If the Default Memory Control Register (DMCR)
control bits are used, no chip select or DRAM control signals
are asserted during the transfer.
9.3.1.2 ACCESS PERMISSIONS. Chip select accesses can be restricted based on
transfer direction and attributes. Each chip select can be enabled for read and/or write
transfers using the WR and RD bits in the CSCRs. Each chip select can have supervisor
data, supervisor code, user data, user code, and only chip select 1 can have CPU space
(including interrupt acknowledge) transfers masked from their address space using the
SD, SC, UD, UC, and C/I bits in the CSMRs. The transfer address must match, the
transfer direction must be enabled, and transfer attributes must be unmasked for a chip
select to assert.
9.3.1.3 CONTROL FEATURES. The chip select control registers and the default
memory control register are used to program timing and assertion features of the chip
selects. The chip select control register provides the following programmable control
features:
• Port size (8-, 16- or 32-bit)
• Number of internal wait states (0 - 15)
• Enable assertion of internal transfer acknowledge
• Enable assertion of transfer acknowledge for external master transfers
• Enable burst transfers
Table 9-3. Chip Select, DRAM and Default Memory Address Decoding Priority
Chip Select 0
Chip Select 1
Chip Select 2
Chip Select 3
Chip Select 4
Chip Select 5
Chip Select 6
Chip Select 7
DRAM bank 0
DRAM bank 1
default memory
Highest priority
Lowest priority
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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