Datasheet

Chip Select Module
MOTOROLA MCF5206e USER’S MANUAL 9-7
• Address setup
• Address hold
• Enable read and/or write transfers
9.3.1.3.1 8-, 16-, and 32-Bit Port Sizing. The general-purpose chip selects support
static bus sizing. You can program the size of the port controlled by a chip select. Defined
8 bit ports are connected to D[31:24]; defined 16-bit ports are connected to D[31:16]; and
defined 32 bit ports are connected to D[31:0]. The port size is specified by the PS bits in
the CSCR.
9.3.1.3.2 Termination. The general-purpose chip selects support three methods of
termination: internal termination, synchronous termination, and asynchronous
termination. You can program the number of wait states required for each chip select and
the default memory individually. You can also enable internal termination for MCF5206e-
initiated transfers for each chip select and default memory individually.
Transfer acknowledge (TA) can synchronously terminate a transfer. If the MCF5206e
initiates a bus transfer and internal termination is enabled (but TA is asserted before the
specified number of wait states have been inserted), the transfer terminates on the CLK
cycle where TA is asserted.
NOTE
If an external master initiates a bus transfer and internal
termination is enabled, TA should not be driven by an external
device. The MCF5206e drives TA throughout the external
master access.
Asynchronous transfer acknowledge (ATA) can asynchronously terminate a chip select or
default memory transfer. If the MCF5206e initiates a bus transfer and internal termination
is enabled but ATA is asserted before the specified number of wait states have been
inserted, the transfer terminates on the CLK cycle where the internal asynchronous
transfer acknowledge is asserted. If an external master initiates a bus transfer and internal
termination is enabled, ATA can be driven by an external device to terminate the transfer
before the specified number of wait states has been inserted. In this case, the transfer
terminates when the internal asynchronous transfer acknowledge is asserted.
9.3.1.3.3 Bursting Control. The general-purpose chip selects support burst and non-
bursting peripherals and memory. If an external chip select device cannot be accessed
using burst transfers, you can program the burst-enable bit in the appropriate chip select
Control Register (CSCR) or in the Default Memory Control Register (DMCR) to a 0. If the
burst-enable bit is set to 1, burst transfers are generated anytime the requested operand
size is greater than the programmed chip select or default memory port size. If the burst
enable bit is set to 0, nonburst transfers are always generated for the particular chip select
or default memory access. Figure 9-5, Figure 9-6, and Figure 9-7 illustrate burst transfers
with various settings of address setup, address hold, and 0 wait states.
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Freescale Semiconductor, Inc.
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