Datasheet

Chip Select Module
9-8 MCF5206e USER’S MANUAL MOTOROLA
9.3.1.3.4 Address Setup and Hold Control. The timing of the assertion and negation of
the general-purpose chip selects and write enables can be programmed on a chip select
basis. You can program each chip select to assert when the clock transfer start (TS) is
asserted or assert the CLK cycle after transfer start (TS) is asserted. For burst transfers,
you can select if the chip select remains valid while the burst address is incremented. You
can also program the address, attribute, and data (if the transfer is a write) to remain
driven and valid for an additional CLK cycle after the transfer is terminated. Figures 9-2,
9-3, and 9-4 illustrate three transfers with various settings.
9.3.2 Global Chip Select Operation
CS[0] is the global (boot) chip select and as such, allows address decoding for boot ROM
before system initialization occurs. Its operation differs from the other external chip select
outputs following a system reset. After system reset, CS[0] is asserted for all accesses
except for CPU space accesses (including MOVEC transfers and interrupt acknowledge
cycles), and internal peripheral accesses. This capability allows the boot ROM to be
located at any address in the external address space. CS[0] operates in this manner until
CSMR0 is written.
The port size and automatic acknowledge functions of CS[0] are determined by the logic
level on pins IRQ1, IRQ4, and IRQ7 sampled on the last rising edge of CLK that RSTI is
asserted (see Bus Operations Section 6.11 Reset Operation).
At system reset, CS[0] allows read and write transfers with address setup, read and write
address-hold enabled, and bursting disabled. Writes to CSCR0 do not deactivate the
global chip select function; therefore, the number of wait states, read and write enable,
address setup, read and write address hold enable, and burst-enable may be changed.
The global chip select functionality is disabled on the first write to CSMR0 after reset. You
should set up the appropriate chip select, DRAM, and default memory control registers
before writing a 1 to CSMR0. Once CSMR0 has been written, the global chip select
functionality can be reactivated only by reset.
9.3.3 General Chip Select Operation
The MCF5206e uses the address bus (A[27:0]) to specify the location for a data transfer
and the data bus (D[31:0]) to transfer the data. Chip selects are asserted during bus
transfers where the address, transfer direction and type are not masked for the particular
chip select. Write enables are asserted on write transfers and indicate the valid byte lanes
for the transfer. Write enables are always asserted on the CLK cycle after the chip select
is asserted.
Chip select and write enables can be asserted during burst and burst inhibited transfers.
The assertion and negation timing of the chip selects are controlled by the address setup,
read address hold, and write address hold bits in the chip select control registers.
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