Datasheet

Chip Select Module
MOTOROLA MCF5206e USER’S MANUAL 9-9
9.3.3.1 NONBURST TRANSFER WITH NO ADDRESS SETUP AND NO ADDRESS
HOLD. Figure 9-2 illustrates a supervisor data longword write transfer to a 32-bit port. In
this case, address setup and write address hold features are disabled.
.
Figure 9-2. Longword Write Transfer from a 32-Bit Port (No Wait State, No Address
Setup, No Address Hold)
Clock 1 (C1)
The write cycle starts in C1. During C1, the MCF5206e places valid values on the address
bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the
specific access type and access type and mode (ATM) is driven low to identify the transfer
as data. The read/write (R/W) signal is driven low for a write cycle, and the size signals
(SIZ[1:0]) are driven low to indicate a longword transfer. The MCF5206e asserts transfer
start (TS) to indicate the beginning of a bus cycle and asserts the appropriate chip select
(CS
) for the address being accessed.
Clock 2 (C2)
TS
A[27:0]
R/W
CLK
TT[1:0]
ATM
TA
D[31:0]
TEA
SIZ[1:0]
C1 C2
$0
$0
$ADDR
ATA
CS
WE[3:0]
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eescale S
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