Datasheet

LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
xxii MCF5206e USER’S MANUAL MOTOROLA
6-25. Burst-Inhibited Word Read from 8 bit Port Using Async. Termination........... 6-43
6-26. Burst-Inhibited Word-, Longword-, and Line-Write Transfer Flowchart ..........6-45
6-27. Burst-Inhibited Longword-Write Transfer to 16 bit Port ..................................6-46
6-28. Example of a Misaligned Longword Transfer .................................................6-48
6-29. Example of a Misaligned Word Transfer ........................................................6-48
6-30. Interrupt Acknowledge Cycle Flowchart......................................................... 6-50
6-31. Interrupt Acknowledge Bus Cycle Timing (No Wait States)........................... 6-51
6-32. Bursting Longword-Read Access from 16 bit Port ........................................ 6-53
6-33. MCF5206e Two-Wire Mode Bus Arbitration Interface ................................... 6-55
6-34. Two-Wire Implicit and Explicit Bus Ownership............................................... 6-57
6-35. Two-Wire Bus Arbitration with Bus Lock Negated ......................................... 6-58
6-36. Two-Wire Bus Arbitration with Bus Lock Asserted......................................... 6-59
6-37. MCF5206e Two-Wire Bus Arbitration Protocol State Diagram...................... 6-60
6-38. Three-Wire Implicit and Explicit Bus Ownership............................................ 6-63
6-39. Three-Wire Bus Arbitration with Bus Lock Bit Asserted................................. 6-64
6-40. MCF5206e Bus Arbitration Protocol State Diagram ...................................... 6-65
6-41. Alternate Master Read Transfer using MCF5206e-Generated
Transfer Acknowledge Flowchart................................................................... 6-70
6-42. Alternate Master Read Transfer......................................................................6-71
6-43. Alternate Master Write Transfer..................................................................... 6-72
6-44. Alternate Master Write Transfer Using Transfer-Acknowledge Timing .........6-73
6-45. Alternate Master Bursting Read Transfer Flowchart ......................................6-75
6-46. Alternate Master Bursting Longword Read Transfer to an 8 bit Port ............6-76
6-47. Alternate Master Bursting Write Transfer Flowchart...................................... 6-79
6-48. Alternate Master Bursting Longword Write Transfer to a 16 bit Port ............. 6-80
6-49. Master Reset Timing...................................................................................... 6-82
6-50. Normal Reset Timing ..................................................................................... 6-83
6-51. Software Watchdog Timer Reset Timing .......................................................6-84
7-1. DMA Signal Diagram ....................................................................................... 7-2
7-2. Single-Address Transfers ................................................................................ 7-5
7-3. Dual-Address Transfer..................................................................................... 7-5
7-4. DMA Controller Module Register Model Per Channel ..................................... 7-6
7-5. External Request Timing - Cycle-Steal Mode, Single-Address Mode............ 7-15
7-6. External Request Timing - Cycle-Steal Mode, Dual-Address Mode .............. 7-16
9-1. MCF5206e Interface to Various Port Sizes...................................................... 9-4
9-2. Longword Write Transfer from a 32 bit Port .................................................... 9-9
9-3. Word Write Transfer to a 16 bit Port ...............................................................9-10
9-4. Byte Write Transfer from an 8 bit Port ..........................................................9-12
9-5. Longword Burst Read Transfer from a 16 bit Port .........................................9-14
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