Datasheet

Chip Select Module
9-10 MCF5206e USER’S MANUAL MOTOROLA
During C2, the MCF5206e negates transfer start (TS), drives access type and mode
(ATM) high to identify the transfer as supervisor and drives data onto D[31:0]. If the
selected device(s) is ready to latch the data, it latches D[31:0] and asserts the transfer
acknowledge (TA). At the end of C2, the MCF5206e samples the level of TA. If TA is
asserted, the transfer of the longword is complete, and the MCF5206e negates CS and
WE[3:0] after the next rising edge of CLK. If TA is negated, the MCF5206e continues to
sample TA and inserts wait states instead of terminating the transfer. The MCF5206e
continues to sample TA on successive rising edge of CLK until it is asserted. If the bus
monitor timer is enabled and TA is not asserted before the programmed bus monitor time
is reached, the cycle is terminated with an internal bus error.
9.3.3.2 NONBURST TRANSFER WITH ADDRESS SETUP. Figure 9-3 illustrates a
word user data write transfer to a 16-bit port with address setup enabled..
Figure 9-3. Word Write Transfer to a 16-Bit Port (One Wait State, Address Setup, No
Address Hold)
TS
A[27:0]
R/W
CLK
TT[1:0]
ATM
TA
D[31:16]
TEA
SIZ[1:0]
C1 C2
$2
$0
$ADDR
ATA
CS
WE[1:0]
C3
ADDRESS
SETUP
WE
[3:2]
WAIT
STATE
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eescale S
emiconduct
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Freescale Semiconductor, Inc.
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