Datasheet

Chip Select Module
MOTOROLA MCF5206e USER’S MANUAL 9-11
Clock 1 (C1)
The write cycle starts in C1. During C1, the MCF5206e places valid values on the address
bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the
specific access type and access type and mode (ATM) is driven low to identify the transfer
as data. The read/write (R/W
) signal is driven low for a write cycle, and the size signals
(SIZ[1:0]) are driven to $2 to indicate a word transfer. The MCF5206e asserts transfer
start (TS
) to indicate the beginning of a bus cycle. The chip select (CS) signal is driven
high since the appropriate address setup bit in the chip select control register is set to 1.
Clock 2 (C2)
During C2, the MCF5206e negates transfer start (TS
), drives access type and mode
(ATM) low to identify the transfer as user and drives data onto D[31:16] and asserts the
appropriate chip select (CS
) signal. At the end of C2, the MCF5206e samples the level of
TA. If TA was asserted the transfer of the word would be complete. Since TA is negated,
the MCF5206e continues to output the data and inserts a wait state instead of terminating
the transfer.
Clock 3 (C3)
The MCF5206e asserts the write enable (WE[1:0]) signals. If the selected device(s) is
ready to latch the data, it latches D[31:0] and asserts the transfer acknowledge (TA). At
the end of C3, the MCF5206e samples the level of TA . If TA is asserted, the transfer of
the word is complete, and the MCF5206e negates CS and WE[1:0] after the rising edge
of CLK. If TA is negated, the MCF5206e continues to sample TA and inserts wait states
instead of terminating the transfer. The MCF5206e continues to sample TA on successive
rising edge of CLK until it is asserted. If the bus monitor timer is enabled and TA is not
asserted before the programmed bus monitor time is reached, the cycle is be terminated
with an internal bus error.
NOTE
When address setup is enabled (ASET=1), write enables
(WE
[3:0]) do not assert on zero wait state write transfers.
9.3.3.3 NONBURST TRANSFER WITH ADDRESS SETUP AND HOLD. Figure 9-4
illustrates a supervisor data byte write transfer to an 8-bit port with address setup and
write address hold enabled.
Fr
eescale S
emiconduct
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, I
Freescale Semiconductor, Inc.
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