Datasheet

Chip Select Module
9-12 MCF5206e USER’S MANUAL MOTOROLA
.
Figure 9-4. Byte Write Transfer from an 8-Bit Port (One Wait State, Address Setup,
Address Hold)
Clock 1 (C1)
The write cycle starts in C1. During C1, the MCF5206e places valid values on the address
bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the
specific access type and access type and mode (ATM) is driven low to identify the transfer
as data. The read/write (R/W) signal is driven low for a write cycle, and the size signals
(SIZ[1:0]) are driven to $1 to indicate a byte transfer. The MCF5206e asserts transfer start
(TS
) to indicate the beginning of a bus cycle. The chip select (CS) signal is driven high
since the appropriate address setup bit in the chip select control register is set to 1.
Clock 2 (C2)
TS
A[27:0]
R/W
CLK
TT[1:0]
ATM
TA
D[31:16]
TEA
SIZ[1:0]
C1 C2
$1
$0
$ADDR
ATA
CS
WE[0]
C3
C4
WE
[3:1]
ADDRESS
SETUP
ADDRESS
HOLD
WAIT
STATE
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
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