Datasheet

Chip Select Module
MOTOROLA MCF5206e USER’S MANUAL 9-13
During C2, the MCF5206e negates transfer start (TS), drives access type and mode
(ATM) high to identify if the transfer as supervisor, drives data onto D[31:16] and asserts
the appropriate chip select (CS). At the end of C2, the MCF5206e samples the level of
TA. If TA was asserted the transfer of the word would be complete. Since TA is negated,
the MCF5206e continues to output the data and inserts a wait state instead of terminating
the transfer.
Clock 3 (C3)
The MCF5206e asserts the write enable (WE[1:0]) signals. If the selected device(s) is
ready to latch the data, it latches D[31:0] and asserts the transfer acknowledge (TA). At
the end of C3, the MCF5206e samples the level of TA. If TA is asserted, the transfer of
the word is complete. If TA is negated, the MCF5206e continues to sample TA and inserts
wait states instead of terminating the transfer. The MCF5206e continues to sample TA on
successive rising edge of CLK until it is asserted. If the bus monitor timer is enabled and
TA is not asserted before the programmed bus monitor time is reached, the cycle is
terminated with an internal bus error.
Clock 4 (C4)
The MCF5206e negates the chip select (CS) and write enable (WE[1:0]) signals and
continues to drive the address, data and attribute signals until after the next rising edge of
CLK.
NOTE
When address setup is enabled (ASET=1), write enables
(WE[3:0]) do not assert on zero wait state write transfers.
9.3.3.4 BURST TRANSFER AND CHIP SELECTS. If the burst enable bit in the
appropriate control register (Chip Select Control Register or Default Memory Control
Register) is set to 1, and the operand size is larger than the port size of the memory being
accessed, the MCF5206e performs word, longword and line transfers in burst mode.
When burst mode is selected, the size of the transfer (indicated by SIZ[1:0]) reflects the
size of the operand being read - not the size of the port being accessed (i.e. a line transfer
is indicated by SIZ[1:0] = $3 and a longword transfer is indicated by SIZ[1:0] = $0,
regardless of the size of the port or the number of transfers required to access the data).
The MCF5206e supports burst-inhibited transfers for memory devices that are unable to
support bursting. For this type of bus cycle, the burst enable bit in the Chip Select Control
Registers (CSCRs) or Default Memory Control Register (DMCR) must be cleared.
Figure 9-5 illustrates a supervisor code longword read transfer to a 16-bit port with
address setup and address hold disabled.
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Freescale Semiconductor, Inc.
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