Datasheet

Chip Select Module
9-14 MCF5206e USER’S MANUAL MOTOROLA
.
Figure 9-5. Longword Burst Read Transfer from a 16-Bit Port (No Wait States,
No Address Setup, No Address Hold)
Clock 1 (C1)
The burst read cycle starts in C1. During C1, the MCF5206e places valid values on the
address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals
identify the specific access type and access type and mode (ATM) is driven high to identify
the transfer as code. The read/write (R/W
) and write enable (WE[3:0]) signals are driven
high for a read cycle, and the size signals (SIZ[1:0]) are driven low to indicate a longword
transfer. The MCF5206e asserts transfer start (TS
) to indicate the beginning of a bus
cycle and asserts the appropriate chip select (CS) for the address being accessed.
Clock 2 (C2)
During C2, the MCF5206e negates transfer start (TS), drives access type and mode
(ATM) high to identify the transfer as supervisor. The selected device(s) places the
addressed data onto D[31:16] and asserts the transfer acknowledge (TA). At the end of
TS
A[27:0]
R/W
CLK
TT[1:0]
ATM
TA
D[31:16]
TEA
SIZ[1:0]
C1 C2
$0
$0
$ADDR
ATA
CS
WE[3:0]
C3
$ADDR + 2
Fr
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Freescale Semiconductor, Inc.
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