Datasheet

Chip Select Module
MOTOROLA MCF5206e USER’S MANUAL 9-15
C2, the MCF5206e samples the level of TA and if TA is asserted, latches the current value
of D[31:16]. If TA is asserted, the transfer of the first word of the longword is complete. If
TA is negated, the MCF5206e continues to sample TA and inserts wait states instead of
terminating the transfer. The MCF5206e continues to sample TA on successive rising
edge of CLK until it is asserted. If the bus monitor timer is enabled and TA is not asserted
before the programmed bus monitor time is reached, the cycle is terminated with an
internal bus error.
Clock 3 (C3)
During C3, the MCF5206e increments A[1:0] to indicate the second word in the longword
transfer. The selected device(s) places the addressed data onto D[31:16] and asserts the
transfer acknowledge (TA). At the end of C3, the MCF5206e samples the level of TA and
if TA is asserted, latches the current value of D[31:16]. If TA is asserted, the transfer of
the second word of the longword is complete and the transfer terminates and the chip
select (CS) is negated. If TA is negated, the MCF5206e continues to sample TA and
inserts wait states instead of terminating the transfer. The MCF5206e continues to sample
TA on successive rising edge of CLK until it is asserted. If the bus monitor timer is enabled
and TA is not asserted before the programmed bus monitor time is reached, the cycle is
terminated with an internal bus error.
9.3.3.5 BURST TRANSFER WITH ADDRESS SETUP. Figure 9-6 illustrates a longword
user code read from a 16-bit port with address setup enabled and read address hold
disabled.
Fr
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Freescale Semiconductor, Inc.
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