Datasheet

Chip Select Module
MOTOROLA MCF5206e USER’S MANUAL 9-17
Clock 2 (C2)
During C2, the MCF5206e negates transfer start (TS), drives access type and mode
(ATM) low to identify if the transfer as user. The appropriate chip select (CS) signal is
asserted. The selected device(s) places the addressed data onto D[31:16] and asserts the
transfer acknowledge (TA
). At the end of C2, the MCF5206e samples the level of TA and
if TA
is asserted, latches the current value of D[31:16]. If TA is asserted, the transfer of
the first word of the longword is complete and chip select (CS) is negated after the next
rising edge of CLK. If TA is negated, the MCF5206e continues to sample TA and inserts
wait states instead of terminating the transfer. The MCF5206e continues to sample TA on
successive rising edge of CLK until it is asserted. If the bus monitor timer is enabled and
TA is not asserted before the programmed bus monitor time is reached, the cycle is
terminated with an internal bus error.
Clock 3 (C3)
During C3, the MCF5206e increments A[1:0] to indicate the second word in the longword
transfer. The chip select (CS) signal is driven high since the appropriate address setup bit
in the chip select control register is set to 1.
Clock 4 (C4)
The selected device(s) places the addressed data onto D[31:16] and asserts the transfer
acknowledge (TA). At the end of C4, the MCF5206e samples the level of TA and if TA is
asserted, latches the current value of D[31:16]. If TA is asserted, the transfer of the
second word of the longword is complete and the transfer terminates and the chip select
(CS) is negated. If TA is negated, the MCF5206e continues to sample TA and inserts wait
states instead of terminating the transfer. The MCF5206e continues to sample TA on
successive rising edge of CLK until it is asserted. If the bus monitor timer is enabled and
TA is not asserted before the programmed bus monitor time is reached, the cycle is
terminated with an internal bus error.
NOTE
When address setup is enabled (ASET=1), write enables
(WE
[3:0]) do not assert on zero wait state write transfers.
9.3.3.6 BURST TRANSFER WITH ADDRESS SETUP AND HOLD. Figure 9-7
illustrates a supervisor data word read transfer from an 8-bit port with address setup and
read address hold enabled.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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