Datasheet

Chip Select Module
9-18 MCF5206e USER’S MANUAL MOTOROLA
.
Figure 9-7. Word Burst Read Transfer from an 8-Bit Port (No Wait States, Address
Setup, Address Hold)
Clock 1 (C1)
The burst read cycle starts in C1. During C1, the MCF5206e places valid values on the
address bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals
identify the specific access type and access type and mode (ATM) is driven low to identify
the transfer as reading data. The read/write (R/W) and write enable (WE[3:0]) signals are
driven high for a read cycle, and the size signals (SIZ[1:0]) are driven to $2 to indicate a
word transfer. The MCF5206e asserts transfer start (TS
) to indicate the beginning of a bus
cycle. The chip select (CS
) signal is driven high since the appropriate address setup bit in
the chip select control register is set to 1.
TS
A[27:0]
R/W
CLK
TT[1:0]
ATM
TA
D[31:24]
TEA
SIZ[1:0]
C1
C2
$2
$0
$ADDR
ATA
CS
WE[3:0]
C3
C4
$ADDR + 1
C5
C6
ADDRESS
SETUP
ADDRESS
HOLD
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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