Datasheet

LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
MOTOROLA MCF5206e USER’S MANUAL xxiii
9-6. Longword Burst Read Transfer from a 16 bit Port ..........................................9-16
9-7. Word Burst Read Transfer from an 8 bit Port..................................................9-18
9-8. Alternate Master Longword Read Transfer from a 32 bit Port ........................9-21
9-9. Alternate Master Longword Read Transfer from a 16 bit Port ......................9-23
9-10. Alternate Master Longword Read Transfer from a 16 bit Port ...................... 9-25
9-11. Chip-Select and Write-Enable Assertion with ASET = 0 Timing ....................9-34
9-12. Chip-Select and Write-Enable Assertion with ASET = 1 Timing.................... 9-34
9-13. Address Hold Timing with WRAH = 0 .............................................................9-36
9-14. Address Hold Timing with WRAH = 1 ............................................................9-36
9-15. Address Hold Timing with RDAH = 0 .............................................................9-37
9-16. Address Hold Timing with RDAH = 1 .............................................................9-38
9-17. Default Memory Address Hold Timing with WRAH = 0 ..................................9-41
9-18. Default Memory Address Hold Timing with WRAH = 1 ..................................9-42
9-19. Default Memory Address Hold Timing with RDAH = 0 ...................................9-43
9-20. Default Memory Address Hold Timing with RDAH = 1 ...................................9-43
11-1. MCF5206e Interface to Various Port Sizes.................................................... 11-4
11-2. Address Multiplexing For 8-bit DRAM With 512 Byte Page Size ................... 11-9
11-3. Connection Diagram for 4MByte DRAM with 8 bit Port and 1 KByte Page.. 11-15
11-4. Connection Diagram for 1MByte DRAM with 8 bit Port and 1 KByte Page.. 11-15
11-5. Byte Read Transfers in Normal Mode with 8 bit DRAM ...............................11-17
11-6. Longword Write Transfer in Normal Mode with 16 bit DRAM ...................... 11-19
11-7. Word Write Transfer in Fast Page Mode with 8 Bit DRAM .......................... 11-22
11-8. Longword Read Transfer Followed by a Page Hit Longword Read Transfer in Fast
Page Mode with 32 bit DRAM...................................................................... 11-24
11-9. Word Write Transfer Followed by a Page-Hit Word Write Transfer in Fast Page Mode
with 16 bit DRAM ......................................................................................... 11-26
11-10. Byte Read Transfer Followed by a Page-Miss Byte Read Transfer in Fast Page
Mode with 8 bit DRAM ................................................................................. 11-28
11-11. Bus Arbitration in Fast Page Mode .............................................................. 11-31
11-12. Longword Write Transfer Followed by a Word Read Transfer in Burst Page Mode
with 16 bit DRAM ......................................................................................... 11-33
11-13. Word Read Transfer Followed by a Page Miss Byte Read Transfer in Fast Page
Mode with 8 bit EDO DRAM......................................................................... 11-36
11-14. Alternate Master Byte Read Transfer Followed by Byte Write Transfer in Normal
Mode with 16 bit DRAM ............................................................................... 11-42
11-15. Alt. Master Longword Write Transfer in Normal Mode with 16 bit DRAM ....11-45
11-16. Alt. Master Word Read Transfer in Burst Page Mode with 8 bit DRAM....... 11-48
11-17. Normal Mode DRAM Transfer Timing.......................................................... 11-53
11-18. Fast Page Mode or Burst Page Mode DRAM Transfer Timing.................... 11-54
11-19. Fast Page Mode or Burst Page Mode DRAM Transfer Timing.................... 11-54
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eescale S
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