Datasheet

Chip Select Module
9-20 MCF5206e USER’S MANUAL MOTOROLA
9.3.4 External Master Chip Select Operation
The MCF5206e can monitor bus transfers by other bus masters and assert chip select
and transfer termination signals during these transfers. Assertion of chip select and
termination signals occurs when the bus is granted to another bus master and TS is
asserted by the external master as an input to the MCF5206e. The MCF5206e registers
the value of A[27:0], R/W and SIZ[1:0] on the rising edge of CLK in which TS is asserted.
NOTE
If the pins A[27:24]/CS[7:4]/WE[0:3] are not assigned to
output address signals, a value of $0 is assigned internally to
these signals. Also, TT[1:0] and ATM are not examined during
external master transfers. The mask bits: SC, SD, UC, UD,
and C/I in the Chip Select Mask Registers (CSMR) are not
used during external master transfers.
The MCF5206e examines the address, direction and size of the transfer and on the next
rising edge of CLK, begins assertion of the proper sequence of memory control signals. If
the transfer is decoded to be a chip select address and the chip select is enabled for the
direction of the transfer (read and/or write enabled), the appropriate chip select and write
enables are asserted. If the chip select is enabled for external master automatic
acknowledge, TA is driven and asserted at the appropriate time. The MCF5206e does not
drive address during external bus master accesses that are decoded as chip select or
default memory transfers. The external master must provide the correct address to the
external memory at the appropriate time.
If the address of the transfer is neither a chip select or a DRAM address, the SIM reads
the Default Memory Control Register (DMCR). If the external master automatic
acknowledge (EMAA) bit in the Default Memory Control Register (DMCR) is set, the
MCF5206e drives transfer acknowledge (TA) as an output and asserts transfer
acknowledge after the number of clocks programmed in the wait state bits (WS) in the
Default Memory Control Register (DMCR).
9.3.4.1 EXTERNAL MASTER NONBURST TRANSFER. The general-purpose chip
selects support burst and nonbursting peripherals and memory for external master
accesses. If an external chip select device can not be accessed using burst transfers, you
can program the burst-enable bit in the appropriate Chip Select Control Register (CSCR)
or in the Default Memory Control Register (DMCR) to a 0. If the burst-enable bit is set to
1, and the external master initiates a transfer where the transfer size is greater than the
programmed port size, the MCF5206e asserts the chip select control signals for a burst
transfer. If the burst enable bit is set to 0, the external master should never initiate a
transfer with the size specified as larger than the programmed port size. Figure 9-8
illustrates a longword read transfer initiated by an external master to a 32-bit port.
Fr
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Freescale Semiconductor, Inc.
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