Datasheet

Chip Select Module
9-22 MCF5206e USER’S MANUAL MOTOROLA
complete. If TA is negated, the external master continues to sample TA and inserts wait
states instead of terminating the transfer.
Clock 4 (C4)
At the start of clock 4, the MCF5206e negates CS and TA, completing the external master
transfer. After the next rising edge of CLK, the MCF5206e three states TA. The external
master can assert TS starting another transfer.
9.3.4.2 EXTERNAL MASTER BURST TRANSFER. The timing of the assertion and
negation of the general-purpose chip selects and write enables during external master
accesses can be programmed on a chip select basis. The address setup and hold
features of the chip selects are not used during nonburst external master accesses. The
address setup and hold features can insert CLK cycles where the chip select is negated,
during burst cycles. During external master read transfers, the MCF5206e drives the
activated chip select signal negated for one CLK cycle for each of the address setup and
read address hold bits that are set to 1. During external master write transfers, the
MCF5206e drives the activated chip select signal negated for one CLK cycle for each of
the address setup and write address hold bits that are set to 1. Figure 9-9 illustrates a
bursting longword read transfer from a 16-bit port with no address setup and no address
hold.
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