Datasheet

Chip Select Module
MOTOROLA MCF5206e USER’S MANUAL 9-23
.
Figure 9-9. External Master Longword Read Transfer from a 16-bit Port (No Wait
State, No Address Setup, No Address Hold)
Clock 1 (C1)
The read cycle starts in C1. During C1, the external master places valid values on the
address bus (A[27:0]) and transfer control signals. At the end of C1, the MCF5206e
registers the external master address, read/write and size signals.
Clock 2 (C2)
During C2, the external master negates transfer start (TS). The MCF5206e compares the
external master address to the internal chip select addresses and enables the appropriate
chip select and transfer acknowledge (TA) for assertion.
Clock 3 (C3)
The MCF5206e asserts the appropriate chip select and since the EMAA bit in the
appropriate Chip Select Control Register (CSCR) is set to one and wait states are set to
zero, asserts transfer acknowledge (TA). The selected device drives data onto D[31:16].
At the end of C3, the external master samples the level of TA. If TA is asserted, the
TS
A[27:0]
R/W
CLK
TA
D[31:16]
TEA
SIZ[1:0]
C1 C2
$0
$ADDR
ATA
CS
WE[3:0]
C3 C4
C5
$ADDR + 2
Fr
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Freescale Semiconductor, Inc.
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