Datasheet

Chip Select Module

9-24 MCF5206e USER’S MANUAL MOTOROLA

transfer of the first word of the longword is complete. If TA is negated, the external master

continues to sample TA and inserts wait states instead of terminating the transfer.

Clock 4 (C4)

At the start of clock 4, the external master increments the address to indicate the second

word of the longword transfer. The MCF5206e continues to assert CS and TA and the

selected slave outputs the data indicated by the new address on D[31:16]. At the end of

clock 4, the external master samples the level of TA. If TA is asserted, the transfer of the

second word of the longword is complete. If TA is negated, the external master continues

to sample TA and inserts wait states instead of terminating the transfer.

Clock 5 (C5)

At the start of clock 5, the MCF5206e negates CS

and TA, completing the external master

transfer. After the next rising edge of CLK, the MCF5206e three states TA

. The external

master can assert TS starting another transfer.

NOTE

Write enables (WE[3:0]) do not assert on zero wait state

external master write transfers.

9.3.4.3 EXTERNAL MASTER BURST TRANSFER WITH ADDRESS SETUP AND

HOLD. Figure 9-10 illustrates a longword bursting read transfer from a 16-bit port with

either address setup or read address hold enabled.

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Freescale Semiconductor, Inc.

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