Datasheet

Chip Select Module

9-26 MCF5206e USER’S MANUAL MOTOROLA

transfer of the first word of the longword is complete. If TA is negated, the external master

continues to sample TA and inserts wait states instead of terminating the transfer.

Clock 4 (C4)

At the start of clock 4, the external master increments the address to indicate the second

word of the longword transfer. The MCF5206e negates CS and TA.

Clock 5 (C5)

At the start of clock 5, the MCF5206e asserts CS and TA. The selected slave outputs the

data indicated by the address on D[31:16]. At the end of clock 4, the external master

samples the level of TA. If TA is asserted, the transfer of the second word of the longword

is complete. If TA is negated, the external master continues to sample TA and inserts wait

states instead of terminating the transfer.

After the next rising edge of CLK, the MCF5206e negates CS and TA, completing the

external master transfer. After the next rising edge of CLK, the MCF5206e three states

TA. The external master can assert TS starting another transfer.

NOTE

Write enables (WE[3:0]) do not assert on zero wait state

external master write transfers.

9.4 PROGRAMMING MODEL

9.4.1 Chip Select Registers Memory Map

Table 9-4 shows the memory map of all the chip select module registers. The internal

registers in the chip select module are memory-mapped registers offset from the MBAR

address pointer.

The following lists several keynotes regarding the programming model table:

• Addresses not assigned to a register and undefined register bits are reserved for

future expansion. Write accesses to these reserved address spaces and reserved

• The reset value column indicates the register initial value at reset. Certain registers

may be uninitialized at reset, i.e., they may contain random values after reset.

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