Datasheet

Chip Select Module
MOTOROLA MCF5206e USER’S MANUAL 9-29
BA31-BA16 - Base Address
This field defines the base address location of memory dedicated to each chip select.
These bits are compared to ColdFire core address bus bits 31-16 to determine if the chip
select memory is being accessed. During external master accesses these bits are
compared as shown in Table 9-5.
9.4.2.2 CHIP SELECT MASK REGISTER (CSMR0 - CSMR7). Each CSMR determines
the address mask for each of the chip selects as well the definition of which types of
accesses are allowed for these signals. Each CSMR is a 32-bit read/write control register.
CSMR0 is initialized to $00000000 by reset and CSMR7 - CSMR1 are unaffected
(uninitialized) by reset. At reset, CS[0] is activated as the global chip select. A write to
CSMR0 deactivates this function. CSMR1 has an additional control bit CPU that allows
you to mask CPU space (including interrupt acknowledge) transfers.
Table 9-5. BA Field Comparisons for External Master Transfers
BA BIT COMPARED TO CONDITIONS
BA31 - BA28 $0 Always
BA27
$0 A[27]/CS[7]/WE[0] does not output A[27]
A[27] A[27]/CS[7]/WE[0] outputs A[27]
BA26
$0 A[26]/CS
[6]/WE[1] does not output A[26]
A[26] A[26]/CS[6]/WE[1] outputs A[26]
BA25
$0 A[25]/CS
[5]/WE[2] does not output A[25]
A[25] A[25]/CS
[5]/WE[2] outputs A[25]
BA24
$0 A[24]/CS[4]/WE[3] does not output A[24]
A[24] A[24]/CS[4]/WE[3] outputs A[24]
BA23 - BA16 A[23:16] Always
BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000000
RESET:
-----------SCSDUCUD-
1514131211109876543210
0000000 0 0 0* 000000
RESET:
Chip Select Mask Register(CSMR0)
MBAR +$68
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...