Datasheet

Chip Select Module
9-30 MCF5206e USER’S MANUAL MOTOROLA
BAM [31:16] - Base Address Mask
This field defines the chip select block size through the use of address mask bits. Any bit
set to 1 masks the corresponding base address register (CSAR) bit (the base address bit
becomes a ‘‘don’t care’’ in the decode).
0 = Corresponding address bit is used in chip select address decode.
1 = Corresponding address bit is not used in chip select address decode.
C/I, SC, SD, UC, UD - CPU Space, Supervisor Code, Supervisor Data, User Code, User
Data Transfer Mask
These fields allows specific types of transfers to be inhibited from accessing a chip select.
If a transfer mask bit is cleared, a transfer of that type can access the corresponding chip
select. If a transfer mask bit is set to 1, an transfer of that type can not access the
corresponding chip select. The transfer mask bits are:
C/I = CPU space and Interrupt Acknowledge Cycle mask (CS[1] only)
SC = Supervisor Code mask
SD = Supervisor Data mask
UC = User Code mask
UD = User Data mask
BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
----------------
RESET:
----------C/ISCSDUCUD-
1514131211109876543210
000000000 0 -----0
RESET:
Chip Select Mask Register(CSMR1)
MBAR +$74
BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
----------------
RESET:
-----------SCSDUCUD-
1514131211109876543210
0000000 0 0 0 0----0
RESET:
Chip Select Mask Register(CSMR2 - CSMR7)
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