Datasheet

Chip Select Module
MOTOROLA MCF5206e USER’S MANUAL 9-31
For each transfer mask bit:
0 = Do not mask this type of transfer for the chip select. A transfer of this type can
occur for this chip select.
1 = Mask this type of transfer from the chip select. If this type of transfer is generated,
this chip select activation is not activated.
NOTE
The C/I, SC, SD, UC, and UD bits are ignored during external
master transfers. Therefore, an external master transfer can
activate a chip select regardless of the transfer masks.
NOTE
In determining whether an external master transfer address
hits in a chip select, the portion of the address bus that is
unavailable externally is regarded as “0's.” That is, the
external master transfer address always has A[31:28] as 0’s
and those bits of A[27:24] that are not programmed to be
external address bits as 0’s. For a chip select to be activated
by an external master, the address bits that are unavailable to
the external master must either be set to 0 in the CSAR or be
masked in the CSMR.
9.4.2.3 CHIP SELECT CONTROL REGISTER (CSCR0 - CSCR7). Each CSCR
controls the acknowledge, external master support, port size, burst and activation
features of each of the chip selects.
Each CSCR is a 16-bit read/write register. For CSCR1 - CSCR7, bits BRST, ASET,
WRAH, RDAH, WR and RD are initialized to 0 by reset while, all other bits are unaffected
(uninitialized) by reset. For CSCR0, bits BRST, and EMAA are initialized to 0 by reset,
while bits WS3 - WS0, ASET, WRAH, RDAH, WR, and RD are initialized to 1 by reset.
The determination of the reset value of bits AA, PS1, and PS0 in the CSCR0 register is
controlled by the logic level at the last rising edge of CLK while reset is asserted, on pins
IRQ7
, IRQ4 and IRQ1, respectively. CS[0] is the global (boot) chip select and as such,
allows address decoding for boot ROM before system initialization occurs. (see Section
6: Bus Operations). Table 9-6 shows how the logic levels on pins IRQ4
and IRQ1
correspond to the port sizes for CS
[0]; Table 9-7 shows the logic levels of IRQ7 to enable
or disable the automatic acknowledge function for CS
[0].
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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