Datasheet

Chip Select Module
9-32 MCF5206e USER’S MANUAL MOTOROLA
WS[3:0] - Wait States
On accesses initiated by the ColdFire core when AA=1, this field de fines the number of
wait states inserted before an internal transfer acknowledge is generated. If TA
is
asserted by the external system before the indicated number of wait states are generated,
the assertion of TA
ends the cycle.
On accesses initiated by an external master when EMAA=1, this field defines the number
of wait states inserted before TA is asserted.
Table 9-6. IRQ4 and IRQ1 Selection of CS[0] Port Size
IRQ4 IRQ1 BOOT CS[0] PORT SIZE
0 0 32-bit port
0 1 8-bit port
1 0 16-bit port
1 1 16-bit port
Table 9-7. IRQ7 Selection of CS[0] Acknowledge Generation
IRQ7 BOOT CS[0] AA
0 Disabled
1 Enabled with 15 wait states
- - WS3 WS2 WS1 WS0 BRST AA PS1 PS0 EMAA ASET WRAH RDAH WR RD
1514131211109876543210
0 0 1 1 1 1 0 IRQ7 IRQ4 IRQ1 011111
RESET:
Chip Select Control Register(CSCR0)
Address MBAR + $6E
- - WS3 WS2 WS1 WS0 BRST AA PS1 PS0 EMAA ASET WRAH RDAH WR RD
1514131211109876543210
00----0----00000
RESET:
Chip Select Control Register(CSCR1-7)
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