Datasheet

Chip Select Module
9-34 MCF5206e USER’S MANUAL MOTOROLA
ASET - Address Setup Enable
This field controls the assertion of chip select with respect to assertion of a valid address.
0 = Assert chip select on the rising edge of CLK that address is asserted. See Figure
9-11.
1 = Delay assertion of chip select for one CLK cycle after address is asserted. See
Figure 9-12.
Figure 9-11. Chip select and Write Enable Assertion with ASET = 0 Timing
Figure 9-12. Chip select and Write Enable Assertion with ASET = 1 Timing
NOTE
WE asserts one clock after the assertion of CS. During write transfers, if ASET = 1, both
CS
and WE are delayed by one clock.
WRAH - Write Address Hold Enable
This field controls the address, data and attribute hold time after the termination (TA
, ATA,
TEA, or internal transfer acknowledge) of a write cycle that hits in the chip select address
space.
CLK
TS
ADDR
CS
WE
CLK
TS
ADDR
CS
WE
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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