Datasheet

Chip Select Module
MOTOROLA MCF5206e USER’S MANUAL 9-37
Figure 9-16. Address Hold Timing with RDAH = 1
WR - Write Enable
This field controls the assertion of chip select and write enable on write cycles.
0 = Disable this chip select during write transfers
1 = Chip select and write enables assert on writes that hit in the chip select address
space
RD - Read Enable
This field controls the assertion of chip select on read cycles.
0 = Disable this chip select during read transfers
1 = Chip select asserts on read transfers that hit in the chip select address space
9.4.2.4 DEFAULT MEMORY CONTROL REGISTER (DMCR). All memory not
associated with the eight chip select address spaces or two DRAM bank address spaces
is considered default memory. The DMCR controls the acknowledge, port size, burst and
address hold features for all default memory space.
The DMCR is a 16-bit read/write register. At system reset, the DMCR is initialized to
$0000.
CLK
TS
ADDR
R/W
CS
WE
TA
DATA
ATTR
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eescale S
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