Datasheet

Chip Select Module
9-38 MCF5206e USER’S MANUAL MOTOROLA
WS[3:0] - Wait States
On accesses initiated by the ColdFire core when AA=1, this field defines the number of
wait states inserted before an internal transfer acknowledge is generated. If TA is
asserted by the external system before the indicated number of wait states are generated,
the external transfer acknowledge ends the cycle.
On accesses initiated by an external master when EMAA=1, this field defines the number
of waits states to be inserted before TA is asserted.
BRST - Burst Enable
This field specifies the burst capability of the default memory space.
0 = Break all transfers that are larger than the specified port size into individual non-
burst transfers that are no larger than the specified port size (e.g. a longword
transfer to an 8-bit port would be broken into four individual byte transfers)
1 = Allow burst transfers to the default memory space for all transfers that are larger
than the specified port size(e.g. longword transfers to 8- and 16-bit ports, word
transfers to 8-bit ports as well as line transfers to 8-, 16- and 32-bit ports)
AA - Auto-Acknowledge Enable for ColdFire Core-Initiated Transfers
This field controls the assertion of the internal transfer acknowledge during accesses
initiated by the ColdFire core that access default memory space.
0 = Wait for external transfer acknowledge for accesses initiated by the ColdFire core
1 = Generate internal transfer acknowledge with the number of wait states specified
by WS[3:0] for accesses initiated by the ColdFire core
If AA=1 and TA is asserted by the external system before the indicated number of wait
states are generated, the assertion of TA
ends the transfer.
NOTE
Since the default memory address space incorporates all
address space not specified as chip select or DRAM address
space, be careful when setting the AA bit in the DMCR. If
AA=1, an access to any address outside of the chip select and
DRAM address spaces is terminated normally with an internal
transfer acknowledge regardless of whether any memory
exists in that location. If you need an Access Fault Exception
to occur when a transfer attempts to access an address
- - WS3 WS2 WS1 WS0 BRST AA PS1 PS0 EMAA - WRAH RDAH - -
1514131211109876543210
0 000000000000000
RESET:
Address MBAR + $C6Default Memory Control Register(DMCR)
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