Datasheet

Chip Select Module
MOTOROLA MCF5206e USER’S MANUAL 9-39
outside of the chip select and DRAM address spaces, set AA
to 0 in the DMCR and enable the Bus Timeout Monitor.
PS[1:0] - Port Size
This field specifies the width of the data associated with the default memory space. It
determines which byte lanes are driven with valid data during write cycles and which byte
lanes are sampled for valid data during read cycles.
EMAA - External Master Automatic Acknowledge Enable
This field controls the driving and assertion of TA during accesses initiated by an external
master.
0 = Do not drive TA as an output during accesses initiated by an external master and
wait for external transfer acknowledge
1 = Drive TA as an output for accesses initiated by an external master and insert the
number of wait states specified by WS[3:0]
NOTE
Because TA is an output when EMAA = 1, TA must not be
driven by the external system. If TA is asserted by the external
system during external master transfer and EMAA = 1,
damage to the part may occur. Refer toSection 6: Bus
Operations for more information on the assertion and driving
of TA during external master accesses.
NOTE
Because the default memory address space incorporates all
address space not specified as chip select or DRAM address
space, be careful when setting the EMAA bit in the DMCR. If
EMAA=1, an access initiated by an external master to any
address outside of the chip select and DRAM address spaces
are terminated normally with an internal transfer acknowledge
regardless of whether any memory exists in that location. If
you need an Access Fault Exception to occur when a transfer
attempts to access an address outside of the chip select and
DRAM address spaces, the external system must provide a
transfer error acknowledge termination, because the internal
Table 9-8. Port Size Encodings
PS[1:0] PORT WIDTH PORTION OF DATA BUS USED
00 32-bit port D[31:0]
01 8-bit port D[31:24]
10 16-bit port D[31:16]
11 16-bit port D[31:16]
Fr
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Freescale Semiconductor, Inc.
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