Datasheet

Chip Select Module
9-40 MCF5206e USER’S MANUAL MOTOROLA
Bus Timeout Monitor does not monitor external master
initiated transfers.
WRAH - Write Address Hold Enable
This field controls the address, data and attribute hold time after the termination (TA, ATA,
TEA, or internal transfer acknowledge) of a write cycle that hits in the default memory
address space.
0 = Do not hold address extra cycle after the transfer is terminated on writes. See
Figure 9-11.
1 = Hold address one cycle after the transfer is terminated on writes. See Figure 9-12.
Figure 9-17. Default Memory Address Hold Timing with WRAH = 0
CLK
TS
ADDR
R/W
CS
WE
TA
DATA
ATTR
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eescale S
emiconduct
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