Datasheet

MOTOROLA MCF5206e USER’S MANUAL 10-1
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SECTION 10
PARALLEL PORT (GENERAL-PURPOSE I/O) MODULE
10.1 INTRODUCTION
The MCF5206e provides eight general-purpose input/output signals that can be used on a
pin-by-pin basis. This subsection describes the operation and programming model of the
parallel port registers and the direction-control and data registers.
10.2 PARALLEL PORT OPERATION
The MCF5206e parallel port module has eight signals that you can select as inputs or
outputs on a pin-by-pin basis. These pins are multiplexed with the MCF5206e emulation
pins and are programmed to their parallel port function through the Pin Assignment Register
(PAR). Refer to the SIM subsection 6.3.2.10 Pin Assignment Register for programming
description.
10.3 PROGRAMMING MODEL
10.3.1 Parallel Port Registers Memory Map
Table 10-1 shows the memory map of all the parallel port registers. The internal registers in
the parallel port module are memory-mapped registers offset from the MBAR address
pointer. Refer to the SIM section for programming of the MBAR.
The following key notes apply to the programming model table:
• Addresses not assigned to a register and undefined register bits are reserved for future
expansion. Write accesses to these reserved address spaces and reserved register bits
have no effect; read accesses return zeros.
• The reset value column indicates the register initial value at reset. Certain registers can
be uninitialized at reset.
• The access column indicates if the corresponding register allows both read/write
functionality (R/W), read-only functionality (R), or write-only functionality (W). Any read-
access attempts to a write-only register will return zeros. A write access to a read-only
register attempt will be ignored and no write will occur.
Table 10-1. Memory Map of Parallel Port Registers
ADDRESS NAME WIDTH DESCRIPTION RESET VALUE ACCESS
MBAR + $1C5 PPDDR 8 Port A Data Direction Register $00 R/W
MBAR + $1C9 PPDAT 8 Port A Data Register $00 R/W
Fr
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Freescale Semiconductor, Inc.
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