Datasheet

Parallel Port (General-Purpose I/O) Module
10-2 MCF5206e USER’S MANUAL MOTOROLA
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10.3.2 Parallel Port Registers
10.3.2.1 PORT A DATA DIRECTION REGISTER (PADDR). The data direction register
allows you to select the signal direction of each parallel port signal. There is one DDR bit in
the PADDR for each parallel port signal. The data direction control bits will only affect the
direction of the associated pin if you program that pin as a general- purpose I/O signal in the
Pin Assigment Register (PAR). Refer to SIM subsection 6.3.2.10 Pin Assigment
Register(PAR) for programming details.
The DDR is an 8-bit read/write register. At system reset, all bits are initialized to zero.
DDR[7:0] - Data Direction Bits[7:0]
For each of the data direction bits, you can select the direction of the signal as follows:
0 = Signal is an input
1 = Signal is an output
Table 10-2 indicates how the bits in the data direction register are assigned to the PP[7:4]/
DDATA[3:0] and PP[3:0]/PST[3:0] signal pins.
10.3.2.2 PORT A DATA REGISTER (PADAT). The parallel port data register reflects the
current status of the parallel port signals. If you configure a parallel port signal as an input,
the value in the register corresponds to the logical voltage level present at the pin. If you
configure the parallel port signal as an output, the value in the register corresponds to the
logical voltage level driven onto the pin.
Table 10-2. Data Direction Register Bit Assignments
DATA DIRECTION REGISTER BIT OUTPUT PIN
DDR7 PP[7]/DDATA[3]
DDR6 PP[6]/DDATA[2]
DDR5 PP[5]/DDATA[1]
DDR4 PP[4]/DDATA[0]
DDR3 PP[3]/PST[3]
DDR2 PP[2]/PST[2]
DDR1 PP[1]/PST[1]
DDR0 PP[0]/PST[0]
DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0
76543210
00000000
RESET:
Data Direction Register (DDR)
Address MBAR + $1C5
R/W
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